Arm DynamIQ Model


The DynamIQ allows compatible cores to be integrated into a multicore system. The DynamIQ integrates 1 to 8 cores with an L3 memory system, control logic, and external interfaces to form a multicore cluster.

The DynamIQ Model allows for up to 4 Big and up to 8 Little core to be configured into a multicore model which includes the DynamIQ Shared Unit (DSU).

The Cortex-A55 Little CPU is supported and the Cortex-A75 Big CPU is supported.

DSU r3p0 supports Cortex-A55 r1p0 and Cortex-A75 r2p1.
DSU r0p2 supports Cortex-A55 r1p0 and Cortex-A75 r2p0.
DSU r0p1 supports Cortex-A55 r0p1 and Cortex-A75 r1p0.

SoC DesignerSystemC ModelSynopsys PA
DynamIQ Cycle Model
Description The DynamIQ model is compiled directly from Arm's register transfer level (RTL) code and maintains 100% functional accuracy. The model integrates directly with Arm's SoC Designer virtual prototype. This enables designers to perform accurate architectural analysis, performance optimization and pre-silicon firmware debug.
Performance Analysis Kits
Revisions r3p0, r0p2, r0p1

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